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Bit
13
Name
TXDMAWU
Reset
0
Access
RW
Description
TX DMA Wakeup
Set to wake the DMA controller up when in EM2 and space is available in the transmit buffer.
Value
0
1
Description
While in EM2, the DMA controller will not get requests about space being available in the transmit buffer
DMA is available in EM2 for the request about space available in the transmit buffer
12
RXDMAWU
0
RW
RX DMA Wakeup
Set to wake the DMA controller up when in EM2 and data is available in the receive buffer.
Value
0
1
Description
While in EM2, the DMA controller will not get requests about data being available in the receive buffer
DMA is available in EM2 for the request about data in the receive buffer
11
BIT8DV
0
RW
Bit 8 Default Value
When 9-bit frames are transmitted, the default value of the 9th bit is given by BIT8DV. If TXDATA is used to write a frame, then the
value of BIT8DV is assigned to the 9th bit of the outgoing frame. If a frame is written with TXDATAX however, the default value is
overridden by the written value.
10
MPAB
0
RW
Multi-Processor Address-Bit
Defines the value of the multi-processor address bit. An incoming frame with its 9th bit equal to the value of this bit marks the frame
as a multi-processor address frame.
9
MPM
0
RW
Multi-Processor Mode
Set to enable multi-processor mode.
Value
0
1
Description
The 9th bit of incoming frames have no special function
An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and
will result in the MPAB interrupt flag being set
8
SFUBRX
0
RW
Start-Frame UnBlock RX
Clears RXBLOCK when the start-frame is found in the incoming data. The start-frame is loaded into the receive buffer.
Value
0
1
Description
Detected start-frames have no effect on RXBLOCK
When a start-frame is detected, RXBLOCK is cleared and the start-frame is loaded into the receive buffer
7
LOOPBK
0
RW
Loopback Enable
Set to connect receiver to LEUn_TX instead of LEUn_RX.
Value
0
1
Description
The receiver is connected to and receives data from LEUn_RX
The receiver is connected to and receives data from LEUn_TX
6
ERRSDMA
0
RW
Clear RX DMA On Error
When set,RX DMA requests will be cleared on framing and parity errors.
Value
0
1
Description
Framing and parity errors have no effect on DMA requests from the LEUART
RX DMA requests from the LEUART are disabled if a framing error or parity error occurs.
5
INV
0
RW
Invert Input And Output
Set to invert the output on LEUn_TX and input on LEUn_RX.
Value
0
1
Description
A high value on the input/output is 1, and a low value is 0.
A low value on the input/output is 0, and a high value is 0.
4
STOPBITS
0
RW
Stop-Bit Mode
Determines the number of stop-bits used. Only used when transmitting data. The receiver only verifies that one stop bit is present.
Value
0
1
Mode
ONE
TWO
Description
One stop-bit is transmitted with every frame
Two stop-bits are transmitted with every frame
2011-04-12 - d0001_Rev1.10
232
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